Reliability challenges of real-time systems in forthcoming technology nodes
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Michael Nicolaidis | Guido Groeseneken | Said Hamdioui | Dimitris Gizopoulos | Arnaud Grasset | Philippe Bonnot | D. Gizopoulos | M. Nicolaidis | Arnaud Grasset | P. Bonnot | G. Groeseneken | S. Hamdioui
[1] G. Groeseneken,et al. Atomistic approach to variability of bias-temperature instability in circuit simulations , 2011, 2011 International Reliability Physics Symposium.
[2] N. Horiguchi,et al. Response of a single trap to AC negative Bias Temperature stress , 2011, 2011 International Reliability Physics Symposium.
[3] Guido Groeseneken,et al. New insights in the relation between electron trap generation and the statistical properties of oxide breakdown , 1998 .
[4] B. Cheng,et al. Advanced simulation of statistical variability and reliability in nano CMOS transistors , 2008, 2008 IEEE International Electron Devices Meeting.
[5] Alessandro Strano,et al. Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration , 2011, ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors.
[6] R. Degraeve,et al. Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS technologies , 2010, 2010 Proceedings of the European Solid State Device Research Conference.
[7] W. Mckee,et al. Leakage and breakdown reliability issues associated with low-k dielectrics in a dual-damascene Cu process , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).
[8] N. Horiguchi,et al. Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).
[9] A. Asenov,et al. The relevance of deeply-scaled FET threshold voltage shifts for operation lifetimes , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).
[10] Francisco J. Cazorla,et al. On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments , 2012, TACO.
[11] Heather M. Quinn,et al. Vision for cross-layer optimization to address the dual challenges of energy and reliability , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[12] J. Suehle. Ultrathin gate oxide reliability: physical models, statistics, and characterization , 2002 .
[13] R. Degraeve,et al. Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices , 2012, IEEE Transactions on Electron Devices.
[14] Lorena Anghel,et al. Cost reduction and evaluation of temporary faults detecting technique , 2000, DATE '00.
[15] J. W. McPherson,et al. A model for stress‐induced metal notching and voiding in very large‐scale‐integrated Al–Si (1%) metallization , 1987 .
[16] Michael Nicolaidis. Design for soft-error robustness to rescue deep submicron scaling , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[17] G. Groeseneken,et al. From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.
[18] T. Grasser,et al. Statistics of Multiple Trapped Charges in the Gate Oxide of Deeply Scaled MOSFET Devices—Application to NBTI , 2010, IEEE Electron Device Letters.
[19] A. Asenov. Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .
[20] Francisco J. Cazorla,et al. Towards improved survivability in safety-critical systems , 2011, 2011 IEEE 17th International On-Line Testing Symposium.
[21] S. Rauch,et al. Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations , 2007, IEEE Transactions on Device and Materials Reliability.
[22] Yu Cao,et al. A resilience roadmap , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[23] Michael Nicolaidis. Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[24] David M. Bull,et al. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.
[25] Shigeo Ogawa,et al. Interface‐trap generation at ultrathin SiO2 (4–6 nm)‐Si interfaces during negative‐bias temperature aging , 1995 .
[26] Sani R. Nassif,et al. A resilience roadmap: (invited paper) , 2010, DATE 2010.
[27] Ming Zhang,et al. Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).
[28] Chenming Hu,et al. Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.
[29] Sanjay Pant,et al. A self-tuning DVS processor using delay-error detection and correction , 2005, IEEE Journal of Solid-State Circuits.
[30] David Blaauw,et al. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.
[31] Shohaib Aboobacker. RAZOR: circuit-level correction of timing errors for low-power operation , 2011 .
[32] Chenming Hu,et al. Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.
[33] V. Huard,et al. NBTI degradation: From transistor to SRAM arrays , 2008, 2008 IEEE International Reliability Physics Symposium.
[34] R. Degraeve,et al. Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.
[35] J. Black,et al. Electromigration—A brief survey and some recent results , 1969 .
[36] A. Hikavyy,et al. Superior NBTI reliability of SiGe channel pMOSFETs: Replacement gate, FinFETs, and impact of Body Bias , 2011, 2011 International Electron Devices Meeting.
[37] Subhasish Mitra,et al. Circuit failure prediction to overcome scaled CMOS reliability challenges , 2007, 2007 IEEE International Test Conference.
[38] Paolo A. Aseron,et al. A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance , 2011, IEEE Journal of Solid-State Circuits.
[39] G. Groeseneken,et al. Time and workload dependent device variability in circuit simulations , 2011, 2011 IEEE International Conference on IC Design & Technology.