MOS Current Mode Logic Near Threshold Circuits

Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET) technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

[1]  Mohamed I. Elmasry,et al.  MOS current mode logic: design, optimization, and variability , 2004, IEEE International SOC Conference, 2004. Proceedings..

[2]  K.J. Kuhn,et al.  Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS , 2007, 2007 IEEE International Electron Devices Meeting.

[3]  Gaetano Palumbo,et al.  Feature - Power-aware design techniques for nanometer MOS current-mode logic gates: a design framework , 2006, IEEE Circuits and Systems Magazine.

[4]  Maitham Shams,et al.  A symmetric mos current-mode logic universal gate for high speed applications , 2007, GLSVLSI '07.

[5]  Emre Salman,et al.  High Performance Integrated Circuit Design , 2012 .

[6]  Eby G. Friedman,et al.  Simultaneous switching noise in on-chip CMOS power distribution networks , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[8]  Roy Paily,et al.  Study of Transistor Mismatch in Differential Amplifier at 32 nm CMOS Technology , 2011 .

[9]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[10]  Mohamed I. Elmasry,et al.  MOS current mode circuits: analysis, design, and variability , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Mohd. Hasan,et al.  Energy Efficient and Process Tolerant Full Adder Design in Near Threshold Region Using FinFET , 2010, 2010 International Symposium on Electronic System Design.

[12]  Dirk Herrmann,et al.  Three Dimensional Integrated Circuit Design , 2016 .

[13]  Volkan Kursun,et al.  FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[14]  Mark Anders,et al.  Near-threshold voltage (NTV) design — Opportunities and challenges , 2012, DAC Design Automation Conference 2012.