Charging studies using the CHARM2 wafer surface charging monitor

Abstract A second generation wafer surface potential monitor (CHARM2) employing floating gate EEPROM transistors as sensing/ memory elements is described, and applied to the study of charging behavior of bare and patterned-resist-covered wafers during high-current arsenic implants. Analysis of the data supports the occurrence of both positive and negative charging transients. Moreover, the destructive power of the positive transient increases many orders of magnitude in the case of resist-covered wafers.