An Efficient Architecture for Interleaved Modular Multiplication
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[1] Q. K. Kop,et al. Fast algorithm for modular reduction , 1998 .
[2] Christof Paar,et al. Efficient hardware architectures for modular multiplication on FPGAs , 2005, International Conference on Field Programmable Logic and Applications, 2005..
[3] G. R. Blakley,et al. A Computer Algorithm for Calculating the Product AB Modulo M , 1983, IEEE Trans. Computers.
[4] P. L. Montgomery. Modular multiplication without trial division , 1985 .
[5] Manfred Schimmler,et al. Area and time efficient modular multiplication of large integers , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.
[6] David Narh Amanor,et al. Efficient Hardware Architectures for Modular Multiplication , 2005 .