Functional verification methodology of Chameleon processor

Functional verification of the new generation microprocessor developed by SGS-Thomson Microelectronics makes extensive use of advanced technologies. This paper presents a global overview of the methodology and focuses on three main aspects: Use of acceleration and emulation technologies for the verification of the VRDL specification in the early stages of the design; development and use of sequential verification methods built upon a commercially available formal proof tool; and extensive use of combinational proof for circuit-level verification, in conjunction with transistor abstraction.