Enhancing the performance of multi-cycle path analysis in an industrial setting

We enhance the performance of multicycle path analysis in an industrial setting. Industrial designs are, in general, more complicated, but contain more information than fundamental sequential circuits. We show how such information is used for improving the quality and the efficiency of multicycle path analysis. Specifically, we propose local FSM learning to take into account reachability information. We also propose FF enable learning to accelerate multicycle path analysis. Experimental results show that our methods can handle large industrial designs with tens of thousands of FFs and detects more multicycle paths faster than conventional ones.

[1]  Jeffrey D. Ullman,et al.  Introduction to Automata Theory, Languages and Computation , 1979 .

[2]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[3]  Joseph Sifakis,et al.  Automatic Verification Methods for Finite State Systems , 1989, Lecture Notes in Computer Science.

[4]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[5]  David Hung-Chang Du,et al.  Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[6]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[7]  Yusuke Matsunaga,et al.  Enhanced Unique Sensitization for Efficient Test Generation (Special Issue on Synthesis and Verification of Hardware Design) , 1993 .

[8]  Sharad Malik,et al.  Computation of floating mode delay in combinational circuits: theory and algorithms , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Robert K. Brayton,et al.  Delay Models and Exact Timing Analysis , 1993 .

[10]  Anurag P. Gupta Timing verification of microprocessor-based designs , 1994 .

[11]  Daniel P. Siewiorek,et al.  Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-based Designs , 1994, 31st Design Automation Conference.

[12]  Sharad Malik,et al.  Exploiting multicycle false paths in the performance optimization of sequential logic circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Kazuyoshi Takagi,et al.  Waiting false path analysis of sequential logic circuits for performance optimization , 1998, ICCAD.

[14]  Kwang-Ting Cheng,et al.  Functionally Testable Path Delay Faults on a Microprocessor , 2000, IEEE Des. Test Comput..

[15]  Shinji Kimura,et al.  Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion , 2000 .

[16]  Hiroyuki Higuchi An implication-based method to detect multi-cycle paths in large sequential circuits , 2002, DAC '02.

[17]  Daniel Brand,et al.  Timing Analysis using Functional Relationships , 2003 .