SINIS process development for integrated circuits with characteristic voltages exceeding 250 /spl mu/V

At PTB, the fabrication process in Nb-Al/Al/sub x/O/sub y//Al/Al/sub x/O/sub y//Al-Nb SINIS multilayer technology has been improved to raise the characteristic voltage of SINIS two-tunnel Josephson junctions up to V/sub C/=I/sub C/R/sub n/=245 /spl mu/V. The process has been realized in LTS implementation. Various sets of the test wafers and wafers containing dc/SFQ and SFQ/dc converters, Josephson transmission lines, and T-flipflop circuits were fabricated and measured. The critical current densities of the junctions have been varied in the range from 70 A/cm/sup 2/ to 2.2 kA/cm/sup 2/ with corresponding characteristic voltages of V/sub C/=55 /spl mu/V and 245 /spl mu/V at the temperature of 4.2 K. The junctions show nearly hysteresis-free behaviour (less than 15%), the intra-wafer parameter spread is smaller than /spl plusmn/10%. RSFQ circuits have been realized with operation margins of the bias currents larger than /spl plusmn/20%.