Soft error stability of p-well versus n-well CMOS latches derived from 2-D transient simulations

Numerical simulations for the response of inverters to high-energy ion strikes are used to compare the single-event-upset (SEU) hardness of p- versus n-well technologies. A constant-geometry, mirror-image technique is used to generate the technology designs, with the objective of presenting features inherent to the well type. The p-well exhibits better SEU tolerance at low ion energies, but in the high-energy regime the two technologies become essentially equivalent. This results from saturation effects known to occur in modern SRAMs (static random access memories).<<ETX>>