STT-Based Non-Volatile Logic-in-Memory Framework

This work describes an integration of logic within the Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) framework. For memory, a minimum separation between the cells is required to ensure bit-to-bit independency. For logic that relies on magnetostatic coupling, a maximum separation is allowed between magnetic cells for effective computation. Integration of the two functionalities therefore requires meeting the orthogonal spatial needs of separation. In this work the technological challenges of this integration are first described followed by the specifications of the new STT-MRAM based logic-in-memory architecture. How a spin transfer torque based control, also called clock, can tune the architecture between logic and memory modes is next described. A reference free variability tolerant differential read scheme leveraging the integration is presented. This logic-in-memory framework is also an integration between magnetic and CMOS planes. Finally, a logic partitioning between the two planes is described that can significantly improve the performance metrics.

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