Design and Modelling of a Low-Latency Centralized Controller for Optical Integrated Networks

Optical integrated network (OIN) is a promising alternative to overcome the restrictions that electrical networks-on-chip (eNoCs) will face in the next generation of multiprocessor integrated systems due to electrical interconnects' physical limitations. OINs present a higher bandwidth and lower power consumption but their full capabilities are curbed by high latency controllers. Control techniques, such as circuit switching, impose a high latency to perform the correct network routing and a better solution must be found in order to fully utilize OINs. In this letter, we have designed and modeled a low-latency centralized controller (LUCC). For validation purposes, we modeled different Mach-Zehnder interferometer (MZI)-based optical interconnects that employ the proposed LUCC. We obtain a response time of only one clock cycle when using the LUCC, even when conflicts are found.

[1]  Alexander V. Rylyakov,et al.  Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers , 2012, IEEE Journal of Solid-State Circuits.

[2]  M. Zamboni,et al.  A multiprocessor based packet-switch: performance analysis of the communication infrastructure , 2005, IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..

[3]  Xi Chen,et al.  Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication , 2011, JETC.

[4]  Luca Benini,et al.  Powering networks on chips , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[5]  Ian O'Connor,et al.  Reduction methods for adapting optical network on chip topologies to 3D architectures , 2013, Microprocess. Microsystems.

[6]  Michal Lipson,et al.  Broadband Operation of Nanophotonic Router for Silicon Photonic Networks-on-Chip , 2010, IEEE Photonics Technology Letters.

[7]  Nick McKeown,et al.  The iSLIP scheduling algorithm for input-queued switches , 1999, TNET.

[8]  Novica Nosovic,et al.  Dijkstra's shortest path algorithm serial and parallel execution performance analysis , 2012, 2012 Proceedings of the 35th International Convention MIPRO.

[9]  Alexander V. Rylyakov,et al.  Monolithic Silicon Integration of Scaled Photonic Switch Fabrics, CMOS Logic, and Device Driver Circuits , 2014, Journal of Lightwave Technology.

[10]  M. Mirshafiei,et al.  MZI-Based Non-blocking SOI Switches , 2014, 2014 Asia Communications and Photonics Conference (ACP).

[11]  V. Benes.  On rearrangeable three-stage connecting networks , 1962 .

[12]  Mike Ignatowski,et al.  Exploitation of optical interconnects in future server architectures , 2005, IBM J. Res. Dev..

[13]  Odile Liboiron-Ladouceur,et al.  Towards a centralized controller for silicon photonic MZI-based interconnects , 2015, 2015 IEEE Optical Interconnects Conference (OI).