Slowing the none-critical path to improve carry look-ahead adder power dissipation

In this paper we use a 4-bit carry look-ahead adder to highlight the contribution by false-starts (glitches) to overall dynamic power dissipation. These false-starts occur in the generation of the sum outputs and are due to delays in generating and propagating the carry signals. We employ sub-threshold transistor operation in the none critical path and reduce power dissipation by 40%. Post layout simulations in a 90 nm technology node have been performed and for 1.8 % increase in transistor count we improve power dissipation by 40 %. It is easy to overlook the amount of power dissipation due to false-starts because input and output latches that are typically employed in most synchronous digital systems/circuits mask these glitches. By sampling the signals after they settle at the desired steady state values we can avoid sending the glitches through latches to the sum outputs. This does not however eliminate the power dissipated by the circuit.