O (log N / log log N) Randomized Routing in Degree-log N "Hypermeshes"

I . 'L 3 Given the clear and pressing need for improved computer system performance, there are several means of achieving this end. In the simplest approach, current computer architectures are reimplemented using faster technologies. Although this approach will 7 always be exploited, physical, technological, and economic limitations make it incapable of providing all the needed compu@ional power. Instead, parallelism must be exploited to obtain m l y significant performance improvements. Parallelism is a two dimensional problem. Along one dimension we find pure data parallelism as might be found in typical army algorithms involving vectors and matrices. Along the other dimension we find concurrency where independent processes work on facets of an algorithm which may not lend themselves to array processing. Id Assuming the use of the fastest reasonable technology, any further increase in performance requires the efficient exploitation of parallelism in one form or another. The performance of computers can be made incrementaliy extensible by exploiting VLSI b technology to builda con~urrent/parallel computers, ensembles of proceSsing nodes connected by a network. Low latency communication elements are required to support fine-grain or medium-grain parallel computation. Communication between nodes of a multicor$uter need not be slower than the communication between the processor and /memory of a conventional computer. A VLSI-Based network controller can provide nodeto-node communication times that approach main memory access times of sequential computers. A VLSI chip is subject to several technological constraints. Whenever each node of a multicomputer system is implemented as a VLSI chip or a printed circuit board, packaging constraints limit the number of connections that can be made available for communication links. Some key issues which must be considered when designing a high \ performance network controller based on VLSI technology are also discussed. New variations on the 2-d mesh interconnection computer which can be implemented