Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs

This paper introduces Ultra-Fine Grain Vdd-Hopping (FINE-VH), an extension of Dynamic Voltage-Frequency Scaling (DVFS) for energy efficient Multi-Processor SoCs (MPSoCs). The proposed technique leverages the working principle of V ddHopping applied at ultra-fine granularity, i.e., within the core, by means of a layout-assisted, level-shifter free, dynamic dual-V dd control strategy where leakage currents are minimized through an optimal timing-driven poly-bias assignment procedure. A dedicated back-end flow implementing FINE-VH has been devised such to guarantee design convergence with minimum area/delay overhead; such a tool is centered tor an industrial Fully-Depleted SOl (FDSOI) CMOS technology at 28nm. Simulation resuIts, conducted on an open-source RISC-V core (the RI5CY core) belonging to an MPSoC platform (the PULP platform), demonstrate FINE-VH allows substantial power savings w.r.t. coarse-grain ideal-DVFS (best-case 32.6%, average 22.9%) and state-of-the-art V dd-Hopping (best-case 60.1 %, average 42.5%) and Vdd-Dithering (best-case 38.3%, average 26.8%).

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