A narrow-to-wideband scrambling technique increasing software radio receiver linearity

Radio receivers and transmitters produce distortion products which are high above the noise floor. These products emanate from a combination of a low-order nonlinearity and the narrowband nature of the signal of interest. In this work, a scrambling system is proposed that can be added to a receiver, reducing these distortion products. Continuous time-domain signal manipulation is used to spread the spectral power of a narrowband signal, before it passes through nonlinear receiver circuitry. Digitally the original signal shape is reconstructed. This way, the distortion created by the nonlinearity does not result in dominant tones, improving IP2 and IP3 figures without increasing the intrinsic circuitry linearity, saving power and maintaining flexibility. This topology became possible through using new designs and topologies, which allow signal manipulation using passive components only. Additionally, a new high speed DAC design allows a voltage supply rail to be used as a sub-mV accurate reference. The concept is demonstrated using a software-radio approach, in which the sampling and buffering represents the nonlinear processing. With a 2.2Vpp, diff 100 MHz input signal, the measured distortion products are below −74 dBc. At 1.4 GHz input this number is 60.2 dBc. The scrambling hardware uses 54 mW in a 65nm CMOS process.

[1]  B. Nauta,et al.  A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 /spl mu/m CMOS [ADC applications] , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[2]  I. Miller Probability, Random Variables, and Stochastic Processes , 1966 .

[3]  Pier Andrea Francese,et al.  A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency , 2009, IEEE Journal of Solid-State Circuits.

[4]  Bram Nauta,et al.  A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[5]  Pier Andrea Francese,et al.  A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Gary Brown,et al.  Linearization of CMOS LNA's via optimum gate biasing , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[7]  Athanasios Papoulis,et al.  Probability, Random Variables and Stochastic Processes , 1965 .