VLSI Yield Prediction and Estimation: A Unified Framework

In this paper we present a unified framework for prediction and estimation of the manufacturing yield of VLSI circuits. We formally introduce a number of yield measures that are useful both during the design process and during the manufacturing process. This framework is general enough to bridge the gap between the traditional concepts of parametric and catastrophic yield. We provide a classification of causes of yield loss which is essential for efficient yield estimation. Finally, we relate yield to manufacturing costs which provides a common denominator for the discussion of the manufacturing process efficiency.

[1]  Wojciech Maly,et al.  Yield estimation model for VLSI artwork evaluation , 1983 .

[2]  Sani R. Nassif,et al.  FABRICS II: A Statistically Based IC Fabrication Process Simulator , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Andrzej J. Strojwas CMU-CAM System , 1985, DAC 1985.

[4]  J. Bernard The IC yield problem: A tentative analysis for MOS/SOS circuits , 1978, IEEE Transactions on Electron Devices.

[5]  C. Stapper Defect density distribution for LSI yield calculations , 1973 .

[6]  Andrzej J. Strojwas,et al.  A Statistical Design Rule Developer , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  J. W. Lathrop,et al.  Defect analysis and yield degradation of integrated circuits , 1974 .

[8]  John Paul Shen,et al.  Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells , 1984, ITC.

[9]  G. Hachtel The simplicial approximation approach to design centering , 1977 .

[10]  O. Paz,et al.  Modification of Poisson statistics: modeling defects induced by diffusion , 1977 .

[11]  Andrzej J. Strojwas,et al.  Statistical Simulation of the IC Manufacturing Process , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  A. V. Ferris-Prabhu,et al.  Defect size variations and their effect on the critical area of VLSI devices , 1985 .

[13]  K. S. Tahim,et al.  A radial exploration approach to manufacturing yield estimation and design centering , 1979 .

[14]  J. Bandler,et al.  Optimal centering, tolerancing, and yield determination via updated approximations and cuts , 1978 .

[15]  E. Polak,et al.  Theoretical and computational aspects of the optimal design centering, tolerancing, and tuning problem , 1979 .

[16]  C. H. Stapper,et al.  A simple method for modeling VLSI yields , 1982 .

[17]  G. Hachtel,et al.  Computationally efficient yield estimation procedures based on simplicial approximation , 1978 .

[18]  M. Lightner Multiple criterion optimization with yield maximization , 1981 .

[19]  P. Balaban,et al.  Statistical analysis for practical circuit design , 1975 .

[20]  Zygmunt Pizlo,et al.  Tolerance Assignment for IC Selection Tests , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  K. Antreich,et al.  Design centering by yield prediction , 1982 .

[22]  T.E. Mangir,et al.  Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI , 1984, Proceedings of the IEEE.

[23]  D. M. H. Walker,et al.  VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  R. R. O'Brien,et al.  A Statistical Approach to the Design of Diffused Junction Transistors , 1964, IBM J. Res. Dev..

[25]  Satoshi Shimada,et al.  Analysis on yield of integrated circuits and a new expression for the yield , 1972 .

[26]  B. T. Murphy,et al.  Cost-size optima of monolithic integrated circuits , 1964 .

[27]  R. Brayton,et al.  Yield maximization and worst-case design with arbitrary statistical distributions , 1980 .

[28]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[29]  Andrzej Strojwas,et al.  PROD: A VLSI Fault Diagnosis System , 1985, IEEE Design & Test of Computers.

[30]  Andrzej J. Strojwas,et al.  Fabrication based statistical design of monolithic IC's , 1981 .

[31]  C. H. Stapper On a composite model to the IC yield problem , 1975 .

[32]  P. J. Rankin Statistical modelling for integrated circuits , 1982 .

[33]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[34]  C. Stapper Yield model for 256K RAMs and beyond , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[35]  Duncan M. Walker Yield simulation for integrated circuits , 1987 .

[36]  Y. Aoki,et al.  CASTAM: A process variation analysis simulator for MOS LSI's , 1984, IEEE Transactions on Electron Devices.

[37]  Andrzej J. Strojwas,et al.  A Pattern Recognition Based Method for IC Failure Analysis , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[38]  Ping Yang,et al.  STATISTICAL MODELING FOR EFFICIENT PARAMETRIC YIELD ESTIMATION , 1983 .

[39]  R. M. Warner Applying a composite model to the IC yield problem , 1974 .

[40]  C. H. Stapper,et al.  Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..

[41]  A. V. Ferris-Prabhu,et al.  Modeling the critical area in yield forecasts , 1985 .