High Linearity and Low Power Cascode CMOS LNA for RF Front End Applications

In this paper, model of low power high linearity CMOS amplifier with low noise figure is presented. LNA is implemented in ADS using TSMC 0.18um technology based on cascode topology with gain boosting technique. In order to improve linearity, feed forward cancellation method is used. The LNA is found to have S11=-0.062dB, S12=-24.239dB, S22=- 1.884dB and noise figure of 3.190dB and IIP3 of 2.6dBm. LNA is consuming 1.34mW of power from 1V power supply and is designed for 2.4GHz ISM band applications.

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