Multibillion packet lookup for next generation networks

Abstract Fast Internet Protocol Version 4 (IPv4) lookup is one of the key challenges that have always been faced with growing internet speed. Next generation networks promise hundreds of gigabit communication bandwidths. To support such high data rates, core networking devices require very fast IPv4 lookup for incoming packets to sustain their functionality. Researchers from academia and industry have contributed widely towards this problem, presenting numerous techniques and algorithms to improve lookup times. In this paper, a bit vector-based IP lookup engine is presented that implements parallel units to achieve 4.3 Billion Packets Per Second (BPPS) lookup speeds for 5 fields. Implementations are done using dual port Distributed RAM (DRAM) on state-of-the-art Xilinx Virtex 7 series Field Programmable Gate Arrays (FPGA). Post place and route results for different configurations showed that the proposed design consumes much less memory, facilitating multiple engines on a single chip whilst maintaining a very low overall power profile.

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