论文信息 - Performance Tradeoffs in Rings of Data-Driven Elements

Performance Tradeoffs in Rings of Data-Driven Elements

A method for maintaining causality within medium grained cellular based architectures is discussed. The strategy combines the benefits of data-driven communication with a hardware simplicity, latency and throughput rate approaching that of globally checked systolic arrays. It is shown that with this strategy higher throughput rates and lower latencies can be achieved by using slower processing elements. >

Andrew Spray | Simon Jones

[1] R. Karp,et al. Properties of a model for parallel computations: determinacy , 1966 .

[2] H. T. Kung. Why systolic architectures? , 1982, Computer.

[3] D. V. Bhaskar Rao,et al. Wavefront Array Processor: Language, Architecture, and Applications , 1982, IEEE Transactions on Computers.

[4] Israel Koren,et al. A data-driven VLSI array for arbitrary algorithms , 1988, Computer.

[5] D.I. Moldovan,et al. On the design of algorithms for VLSI systolic arrays , 1983, Proceedings of the IEEE.

[6] Andrew Spray,et al. PACE: A regular array for implementing regularly and irregularly structured algorithms , 1991 .

[7] R. J. Gal-Ezer,et al. Synchronous Versus Asynchronous Computation In Very Large Scale Integrated (VLSI) Array Processors , 1982, Other Conferences.

[8] G. Mazare,et al. A programmable highly parallel architecture for digital signal processing , 1989, IEEE International Symposium on Circuits and Systems,.

[9] S. Kung,et al. VLSI Array processors , 1985, IEEE ASSP Magazine.