Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model

This paper studies the impact of dummy fill for chemical mechanical polishing (CMP)-induced capacitance variation on buffer insertion based on a virtual CMP fill estimation model. Compared with existing methods, our algorithm is more feasible by performing buffer insertion not in post-process but during early physical design. Our contributions are threefold. First, we introduce an improved fast dummy fill amount estimation algorithm based on [4], and use some speedup techniques (tile merging, fill factor and amount assigning) for early estimation. Second, based on some reasonable assumptions, we present an optimum virtual dummy fill method to estimate dummy position and the effect on the interconnect capacitance. Then the dummy fill estimation model was verified by our experiments. Third, we use this model in early buffer insertion after layer assignment considering the effects of dummy fill. Experimental results verified the necessity of early dummy fill estimation and the validity of our algorithm. Buffer insertion considering dummy fill during early physical design is necessary and our algorithm is promising.

[1]  Yao-Wen Chang,et al.  MR: a new framework for multilevel full-chip routing , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Yici Cai,et al.  Congestion-driven W-shape multilevel full-chip routing framework , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[3]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[4]  Jinjun Xiong,et al.  Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Atsushi Kurokawa,et al.  Dummy filling methods for reducing interconnect capacitance and number of fills , 2005, Sixth international symposium on quality electronic design (isqed'05).

[6]  Weiping Shi,et al.  A fast algorithm for optimal buffer insertion , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Minsik Cho,et al.  Wire Density Driven Global Routing for CMP Variation and Timing , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[8]  Dennis Sylvester,et al.  Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion , 2007, 2007 Asia and South Pacific Design Automation Conference.

[9]  Jiang Hu,et al.  Coupling aware timing optimization and antenna avoidance in layer assignment , 2005, ISPD '05.

[10]  Yici Cai,et al.  Crosstalk driven routing resource assignment , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[11]  Hai Zhou,et al.  Impact of Modern Process Technologies on the Electrical Parameters of Interconnects , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[12]  Andrew B. Kahng,et al.  Monte-Carlo algorithms for layout density control , 2000, ASP-DAC '00.

[13]  Shyh-Chyi Wong,et al.  Modeling of interconnect capacitance, delay, and crosstalk in VLSI , 2000 .

[14]  Martin D. F. Wong,et al.  Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Weiping Shi,et al.  An O(mn) time algorithm for optimal buffer insertion of nets with m sinks , 2006, ASP-DAC.

[16]  Andrew B. Kahng,et al.  Study of floating fill impact on interconnect capacitance , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[17]  Puneet Gupta,et al.  Performance-impact limited area fill synthesis , 2003, DAC '03.

[18]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .

[19]  Charles J. Alpert,et al.  Wire segmenting for improved buffer insertion , 1997, DAC.