A Mixed-Mode Analogue and Switch Level Simulator

This paper describes an experimental mixed-mode simulation system which couples an incremental time analogue simulator to an event-driven switch level simulator. the analogue timing programme uses a variable-step-size, multi-order (VSMO) numerical integration algorithm which detects and uses latency while maintaining wave-form synchronization. the switch level programme uses piecewise linear wave-forms rather than discrete states to model the operation of logical networks. A unified format in which time responses are events is used for communication between the two programmes. the mixed-mode simulator operates without backtracking or translation between logical states and analogue wave-forms.

[1]  J. E. Kleckner.  Advanced mixed-mode simulation techniques , 1984 .

[2]  S. Liu,et al.  Small-signal MOSFET models for analog circuit design , 1982 .

[3]  Chenming Hu,et al.  A compact IGFET charge model , 1984 .

[4]  Alberto L. Sangiovanni-Vincentelli,et al.  Relaxation-based electrical simulation , 1983, IEEE Transactions on Electron Devices.

[5]  Wentai Liu,et al.  Mixed-mode simulation tools for custom VLSI designs , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[6]  C. W. Gear,et al.  Numerical initial value problem~ in ordinary differential eqttations , 1971 .

[7]  Jirí Vlach,et al.  Current-limited switch-level timing simulator for MOS logic networks , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  P. Reynaert,et al.  Mixed-Mode Circuit Simulation Techniques and their Implementation in DIANA , 1984 .

[9]  E. S. Lee,et al.  A mixed-mode analog-digital simulation methodology for full custom designs , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.