Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition
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[1] Zhaowei Zhong,et al. Modal analysis and dynamic responses of board level drop test , 2003, Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003).
[2] C.S. Hsiao,et al. The study of OSP as reliable surface finish of BGA substrate , 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).
[3] Zhaowei Zhong,et al. Impact life prediction modeling of TFBGA packages under board level drop test , 2004, Microelectron. Reliab..
[4] Yi-Shao Lai,et al. Support excitation scheme for transient analysis of JEDEC board-level drop test , 2006, Microelectron. Reliab..
[5] Zhaowei Zhong,et al. Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).
[6] King-Ning Tu,et al. Ductile-to-brittle transition in Sn–Zn solder joints measured by impact test , 2004 .
[7] Y. Mai,et al. Drop Impact: Fundamentals and Impact Characterisation of Solder Joints , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..
[8] Yi-Shao Lai,et al. Transient simulation of solder joint fracturing under impact test , 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).