A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits

We report for the first time a new type of unexpected latch-up phenomenon that can occur in deep sub-micron technologies with the required implementation of voltage tolerant ESD protection circuits. In contrast to the well known Standard latchup, this new latchup, dubbed Signal Latchup, becomes evident only through the interaction from neighboring I/O pins. The issues involved with this latchup effect and the subsequent trade-off with ESD are presented in detail. A new latchup specification is also proposed.

[1]  R. N. Rountree,et al.  Internal chip ESD phenomena beyond the protection circuit , 1988 .

[2]  C. Duvvury,et al.  Integration of TLP analysis for ESD troubleshooting , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[3]  R. N. Rountree,et al.  Internal chip ESD phenomena beyond the protection circuit , 1988 .

[4]  J.W. Miller,et al.  Engineering the cascoded NMOS output buffer for maximum V/sub t1/ , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[5]  Ming-Dou Ker,et al.  Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product , 2002, Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614).

[6]  Ming-Dou Ker,et al.  Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product , 2003, Microelectron. Reliab..

[7]  D. B. Krakauer,et al.  ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration , 1998 .

[8]  C. Duvvury,et al.  An automated tool for detecting ESD design errors , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).