Low-capture-power test generation for scan-based at-speed testing

Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0's and 1's to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield loss

[1]  Lee Song,et al.  Evaluating ATE features in terms of test escape rates and other cost of test culprits , 2002, Proceedings. International Test Conference.

[2]  Nur A. Touba,et al.  Reducing power dissipation during test using scan chain disable , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[3]  Nandu Tendolkar,et al.  Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC/spl trade/ instruction set architecture , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[4]  Atul Patel,et al.  Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  Takaki Yoshida,et al.  MD-SCAN method for low power scan testing , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[6]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[7]  Kuen-Jong Lee,et al.  Peak-power reduction for multiple-scan circuits during test application , 2000, Proceedings of the Ninth Asian Test Symposium.

[8]  Irith Pomeranz,et al.  Techniques for minimizing power dissipation in scan and combinational circuits during test application , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Ozgur Sinanoglu,et al.  Scan power minimization through stimulus and response transformations , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[10]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[11]  L. Whetsel,et al.  An analysis of power reduction techniques in scan testing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[12]  Kozo Kinoshita,et al.  On low-capture-power test generation for scan testing , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[13]  Janusz Rajski,et al.  High-frequency, at-speed scan testing , 2003, IEEE Design & Test of Computers.

[14]  Paolo Prinetto,et al.  A test pattern generation methodology for low power consumption , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[15]  Takaki Yoshida,et al.  A new approach for low-power scan testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[16]  Seongmoon Wang.  Generation of low power dissipation and high fault coverage patterns for scan-based BIST , 2002, Proceedings. International Test Conference.

[17]  Bashir M. Al-Hashimi,et al.  Power-constrained testing of VLSI circuits , 2003 .

[18]  Vishwani D. Agrawal,et al.  Scheduling tests for VLSI systems under power constraints , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[19]  A. Chandra,et al.  Reduction of SOC test data volume, scan power and testing time using alternating run-length codes , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[20]  Sandeep K. Gupta,et al.  ATPG for heat dissipation minimization during test application , 1994, Proceedings., International Test Conference.

[21]  Patrick Girard,et al.  Power driven chaining of flip-flops in scan architectures , 2002, Proceedings. International Test Conference.

[22]  Krishnendu Chakrabarty,et al.  Combining low-power scan testing and test data compression for system-on-a-chip , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[23]  Nur A. Touba,et al.  Controlling peak power during scan testing , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[24]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[25]  Srinivas Patil,et al.  On broad-side delay test , 1994, Proceedings of IEEE VLSI Test Symposium.

[26]  Kohei Miyase,et al.  Test vector modification for power reduction during scan testing , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[27]  Nur A. Touba,et al.  Static compaction techniques to control scan vector power dissipation , 2000, Proceedings 18th IEEE VLSI Test Symposium.