Test-per-clock testing of the circuits with scan

The proposed test-per-clock testing scheme consists of an input scan chain, internal flip-flops, which are concatenated in the scan chain, auxiliary outputs for capturing the signals on the internal CUT outputs and a CUT test response compactor. The proposed method of finding the scan chain sequence uses the previously generated test patterns. The patterns have to contain a maximum number of don't care bits. For this reason we use non-compacted vectors; one vector corresponds to one fault. An algorithm for finding a sub minimal scan chain sequence was developed. The algorithm creates a scan chain sequence that forms on the scan chain flip-flops such vectors that exercise all considered faults of the circuit in a test-per-clock mode. Several experiments were done with ISCAS 85 and 89 benchmark circuits. Compared with the minimized compact test sets the proposed method substantially reduces the test application time, necessary hardware overhead and energy consumption.