Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs

As we approach the limits of 2D device scaling, monolithic 3D IC (M3D) has emerged as a potential solution offering performance and power benefits. Although various studies have been done to increase power savings of M3D designs, efforts to improve their performance are rarely made. In this paper, we, for the first time, perform in-depth analysis of the factors that affect the performance of M3D, and present methodologies to improve the performance. Our methodologies outperform the state-of-the-art M3D design flow by offering 15.6% performance improvement and 16.2% energy-delay product (EDP) benefit over 2D designs.

[1]  Sung Kyu Lim,et al.  Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[2]  Mark Horowitz,et al.  Energy dissipation in general purpose microprocessors , 1996, IEEE J. Solid State Circuits.

[3]  Giovanni De Micheli,et al.  CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[4]  Sung Kyu Lim,et al.  Match-making for Monolithic 3D IC: Finding the right technology node , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  Sung Kyu Lim,et al.  Monolithic 3D IC design: Power, performance, and area impact at 7nm , 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

[6]  Sung Kyu Lim,et al.  Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[7]  Jason Cong,et al.  Thermal-Aware 3D IC Placement Via Transformation , 2007, 2007 Asia and South Pacific Design Automation Conference.

[8]  W. Dehaene,et al.  Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance , 2010, IEEE Electron Device Letters.

[9]  Diederik Verkest,et al.  Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs , 2016, ISLPED.

[10]  Sung Kyu Lim,et al.  Design and CAD methodologies for low power gate-level monolithic 3D ICs , 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).