A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking
暂无分享,去创建一个
[1] James E. Smith,et al. Prefetching in supercomputer instruction caches , 1992, Proceedings Supercomputing '92.
[2] Jan Reineke,et al. Timing predictability of cache replacement policies , 2007, Real-Time Systems.
[3] Dirk Grunwald,et al. Prefetching Using Markov Predictors , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.
[4] Martin Schoeberl,et al. Time-predictable Cache Organization , 2009, 2009 Software Technologies for Future Dependable Distributed Systems.
[5] Jakob Engblom,et al. The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.
[6] Norman P. Jouppi,et al. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[7] Isabelle Puaut,et al. WCET-centric software-controlled instruction caches for hard real-time systems , 2006, 18th Euromicro Conference on Real-Time Systems (ECRTS'06).
[8] Todd C. Mowry,et al. Architectural and compiler support for effective instruction prefetching: a cooperative approach , 2001, TOCS.
[9] Sang Lyul Min,et al. A dual-mode instruction prefetch scheme for improved worst case and average case program execution times , 1993, 1993 Proceedings Real-Time Systems Symposium.
[10] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[11] Wei Zhang,et al. Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time , 2010, IEEE Transactions on Computers.
[12] Peter Marwedel,et al. WCET-aware static locking of instruction caches , 2012, CGO '12.
[13] Yun Liang,et al. WCET-Centric dynamic instruction cache locking , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[14] Trevor N. Mudge,et al. Wrong-path instruction prefetching , 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.
[15] K. Kavi. Cache Memories Cache Memories in Uniprocessors. Reading versus Writing. Improving Performance , 2022 .
[16] Yun Liang,et al. WCET-centric partial instruction cache locking , 2012, DAC Design Automation Conference 2012.
[17] Alan Burns,et al. Writing temporally predictable code , 2002, Proceedings of the Seventh IEEE International Workshop on Object-Oriented Real-Time Dependable Systems. (WORDS 2002).
[18] Alan Jay Smith,et al. Sequential Program Prefetching in Memory Hierarchies , 1978, Computer.
[19] Henrik Theiling,et al. Compile-time decided instruction cache locking using worst-case execution paths , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[20] Víctor Viñals,et al. Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems , 2010, 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications.