1.15 GHz image rejection filter with 45 dB image rejection ratio and 8.4 mW DC power in 90 nm CMOS

Abstract A 1.15 GHz image rejection filter in 90 nm CMOS is presented. It consists of two band-pass filter stages and one band-stop filter stage, with the Q-enhancing and frequency stagger-tuning techniques to compensate the loss of low quality factor on-chip passive components and maintain enough bandwidth, respectively. The presented filter has been integrated in one K-band dual down-conversion super-heterodyne receiver and achieves 45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth. The DC power consumption is 8.4 mW.

[1]  Josef Hausner,et al.  A new Q-enhancement architecture for SAW-less communication receiver in 65-nm CMOS , 2009, 2009 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

[2]  Joohwa Kim,et al.  Staggered Gain for 100+ GHz Broadband Amplifiers , 2011, IEEE Journal of Solid-State Circuits.

[3]  Chinchun Meng,et al.  2.4-GHz $Q$ -Enhanced Lumped Ring Filter With Two Transmission Zeros Using 0.18- $\mu$ m SiGe BiCMOS Process , 2017, IEEE Microwave and Wireless Components Letters.

[4]  Ahmad Mirzaei,et al.  A Low-Power Process-Scalable Super-Heterodyne Receiver With Integrated High-$Q$ Filters , 2011, IEEE Journal of Solid-State Circuits.

[5]  Le Ye,et al.  460 μW 32 dB image rejection ratio second-order active-RC complex filter with improved power efficient opamp , 2013 .

[6]  Robert Bogdan Staszewski,et al.  3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[7]  J.W. Haslett,et al.  2 GHz Automatically Tuned Q-Enhanced CMOS Bandpass Filter , 2007, 2007 IEEE/MTT-S International Microwave Symposium.

[8]  Asad A. Abidi,et al.  CMOS mixers and polyphase filters for large image rejection , 2001, IEEE J. Solid State Circuits.

[9]  Baoyong Chi,et al.  An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Nan Qi,et al.  9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[11]  Fadhel M. Ghannouchi,et al.  2 GHz$rm Q$-Enhanced Active Filter With Low Passband Distortion and High Dynamic Range , 2006, IEEE Journal of Solid-State Circuits.

[12]  F. Svelto,et al.  A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers , 2006, IEEE Journal of Solid-State Circuits.