System Reliability-Aware Energy Optimization for Network-on-Chip with Voltage-Frequency Islands

In this paper, a novel energy optimization algorithm for Network-on-Chip (NoC) based on voltage-frequency islands (VFIs) is proposed under the system reliability constraints. The proposed algorithm mainly includes the three processes of VFI partitioning, assignment and task mapping to reduce the energy consumption. A system reliability-aware mapping algorithm is proposed which employs a hybrid algorithm based on quantum-behaved particle swarm optimization and multi-neighborhood simulated annealing strategy. The optimum particles upon QPSO are further optimized by annealing operation mentioned above. Besides, the catastrophic operation is executed to enlarge the search scope and avoid getting into the local optimum. It minimizes the communication energy consumption of NoC system on the condition of meeting system reliability constraints. Experimental results show that the proposed algorithm is quite effective in optimizing energy consumption of NoC with voltage-frequency islands under system reliability constraints.

[1]  Luca Benini,et al.  Analysis of power consumption on switch fabrics in network routers , 2002, DAC '02.

[2]  Yang Yintang,et al.  Energy Optimization of NoC Based on Voltage-frequency Islands under Processor Reliability Constraints , 2011 .

[3]  David Z. Pan,et al.  A voltage-frequency island aware energy optimization framework for networks-on-chip , 2008, ICCAD 2008.

[4]  Rami G. Melhem,et al.  The effects of energy management on reliability in real-time embedded systems , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[5]  Chi-Ying Tsui,et al.  Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[6]  Ahmed Louri,et al.  Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Tao Gong,et al.  Forma analysis of particle swarm optimisation for permutation problems , 2008 .

[8]  Trevor Mudge,et al.  Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.

[9]  Computing Accurate Performance Bounds for Best Effort Networks-on-Chip , 2013, IEEE Transactions on Computers.

[10]  V. K. Yadav,et al.  Reliable Task Allocation in Heterogeneous Distributed System with Random Node Failure: Load Sharing Approach , 2012, 2012 International Conference on Computing Sciences.

[11]  Petru Eles,et al.  Fault-aware Communication Mapping for NoCs with Guaranteed Latency , 2007, International Journal of Parallel Programming.

[12]  Mahmut T. Kandemir,et al.  Fault tolerant algorithms for network-on-chip interconnect , 2004, IEEE Computer Society Annual Symposium on VLSI.

[13]  Radu Marculescu,et al.  Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[15]  Suleyman Tosun,et al.  Genetic algorithm based NoC design with voltage/frequency islands , 2011, 2011 5th International Conference on Application of Information and Communication Technologies (AICT).

[16]  Arunabha Sen,et al.  Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints , 2010, SAC '10.

[17]  Terrence Mak,et al.  Special issue on emerging on-chip networks and architectures [Editorial] , 2013 .

[18]  D. Marculescu,et al.  Speed and voltage selection for GALS systems based on voltage/frequency islands , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..