Flexible test mode approach for 256-Mb DRAM

This paper describes a flexible test mode approach developed for a 256-Mb dynamic random access memory (DRAM). Test mode flexibility is achieved by breaking down complicated test mode control into more than one primitive test mode. The primitive test modes can be selected together through a WE CAS Before RAS (WCBR) cycle with a series of addresses for mode select. Although each primitive test mode may not complete a meaningful task alone, their combination performs many complex and powerful test modes. In this design, 64 primitive test modes are available. These can be combined to realize more than 19000 useful test modes. A new signal margin test mode is introduced which allows an accurate signal margin test even for small capacitance cells, which are difficult to identify in existing plate-bump method. A flexible multiwordline select test mode effectively performs a toggled wordline disturb test, a long t/sub RAS/ wordline disturb test, and a transfer gate stress voltage test, without causing any unnatural array disturbance. Finally, test modes, which can directly control the timing of sense amplifiers and column select lines, are discussed.

[1]  Masashi Horiguchi,et al.  256-Mb DRAM circuit technologies for file applications , 1993 .

[2]  John K. DeBrosse,et al.  Fault-tolerant designs for 256 Mb DRAM , 1995 .

[3]  Yasunao Katayama,et al.  A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing , 1989 .

[4]  Hideto Hidaka,et al.  An experimental 256-Mb DRAM with boosted sense-ground scheme , 1994 .

[5]  Toshio Sunaga.  A full bit prefetch DRAM sensing circuit , 1996 .

[6]  T. Furuyama,et al.  Wafer burn-in (WBI) technology for RAM's , 1993, Proceedings of IEEE International Electron Devices Meeting.

[7]  Y. Koshikawa,et al.  250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture , 1994 .

[8]  中島 謙,et al.  A 4-level Storage 4Gb DRAM , 1997 .

[9]  M. Wordeman,et al.  Flexible test mode design for DRAM characterization , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[10]  Toshio Takeshima,et al.  A 30-ns 256-Mb DRAM with a multidivided array structure , 1993 .

[11]  K. Kise,et al.  A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[12]  Hiroki Koike,et al.  BIST Circuit Macro Using Microprogram ROM for LSI Memories , 1995 .

[13]  Toshio Takeshima,et al.  A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM , 1990 .

[14]  T. Obara,et al.  250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture , 1993, Symposium 1993 on VLSI Circuits.

[15]  Seung-Hoon Lee,et al.  Skew minimization techniques for 256M-bit synchronous DRAM and beyond , 1996 .

[16]  Hiroki Koike,et al.  A BIST scheme using microprogram ROM for large capacity memories , 1990, Proceedings. International Test Conference 1990.

[17]  S. Kayano,et al.  A 45-ns 64-Mb DRAM with a merged match-line test architecture , 1991 .

[18]  R. Scheuerlein,et al.  A 14-ns 14-Mb CMOS DRAM with 300-mW active power , 1992 .

[19]  Yasunao Katayama,et al.  A pulsed sensing scheme with a limited bit-line swing , 1992 .

[20]  Kenji Natori,et al.  A 60-ns 4-Mbit CMOS DRAM with built-in selftest function , 1987 .

[21]  Takeshi Sakata,et al.  An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture , 1995, IEEE J. Solid State Circuits.

[22]  Jack A. Mandelman,et al.  A 0.6 /spl mu/m/sup 2/ 256 Mb trench DRAM cell with self-aligned BuriEd STrap (BEST) , 1993, Proceedings of IEEE International Electron Devices Meeting.

[23]  Hiroki Koike,et al.  A 30-ns 64-Mb DRAM with built-in self-test and self-repair function , 1992 .

[24]  R. Kleinhenz,et al.  A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond , 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

[25]  Y. Serizawa,et al.  A 256 Mb SDRAM using a register-controlled digital DLL , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[26]  Masahiro Yoshida,et al.  A 17ns 4Mb BICMOS DRAM , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[27]  Yutaka Nakamura,et al.  A full bit prefetch architecture for synchronous DRAM's , 1995 .

[28]  John K. DeBrosse,et al.  A 286 mm/sup 2/ 256 Mb DRAM with /spl times/32 both-ends DQ , 1996 .

[29]  T. Matano,et al.  A 4-level storage 4 Gb DRAM , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.