Network on Chip architecture for BP neural network

Recently, networks-on-chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of artificial neural networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (back-propagation) and evaluated by network-on-chips. Experimental results show that for has a great reduction in communication load and a high connection per second (CPS) compared with traditional BP-ANNs. It is also reconfigurable, expandable and stable to meet various problems.

[1]  Jagath C. Rajapakse,et al.  FPGA Implementations of Neural Networks , 2006 .

[2]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[3]  J. L. Holt,et al.  Back propagation simulations using limited precision calculations , 1991, IJCNN-91-Seattle International Joint Conference on Neural Networks.

[4]  Narayanan Vijaykrishnan,et al.  A generic reconfigurable neural network architecture as a network on chip , 2004, IEEE International SOC Conference, 2004. Proceedings..

[5]  Eugene M. Izhikevich,et al.  Which model to use for cortical spiking neurons? , 2004, IEEE Transactions on Neural Networks.

[6]  Daniel Graupe,et al.  Principles of Artificial Neural Networks , 2018, Advanced Series in Circuits and Systems.

[7]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[8]  Andrew D. Brown,et al.  On-chip and inter-chip networks for modeling large-scale neural systems , 2006, 2006 IEEE International Symposium on Circuits and Systems.