Approximation algorithms for VLSI partition problems

Polynomial time approximation algorithms are described for several VLSI partitioning problems, including graph and hypergraph partitioning, and nonplanar edge deletion. The algorithms find solutions that are within a polylogarithmic factor of the optimal solution for several of the problems. All of the algorithms use the Leighton-Rao (7988) graph-separator algorithm as a subroutine.<<ETX>>