Timing analysis for DCFL/SDCFL VLSI circuits

Abstract A methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input-slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time within 15% error and with a speed-up of four orders of magnitude for several circuits tested as compared with HSPICE simulations.

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