Efficient instruction-level optimization methodology for low-power embedded systems

For low-power embedded systems, we solve the instruction scheduling and reordering problem as a Precedence Constrained Hamiltonian Path Problem for DAGs and the traveling salesman problem (TSP), both of which are NP-hard (W.J. Cook et al., 1998; V. Jain et al., 1999). We propose an efficient instruction-level optimization algorithm for solving the NP-hard problem. Minimum spanning tree (MST) and simulated annealing (SA) mechanisms are used for the optimization. We describe the methods for generating the control flow and data dependence graph (CDG), power dissipation table (PDT), and weighted strongly connected graph (SCG) for the instruction-level low-power analysis. In addition, confidence limits with error tolerance are considered for the validation of the optimization. Finally, experimental results that demonstrate the effectiveness and efficiency of the proposed algorithms are shown.

[1]  William J. Cook,et al.  Combinatorial optimization , 1997 .

[2]  Santosh Pande,et al.  Code restructuring for improving execution efficiency, code size and power consumption for embedded , 1999 .

[3]  Sharad Malik,et al.  Instruction level power analysis and optimization of software , 1996, J. VLSI Signal Process..

[4]  Eugene L. Lawler,et al.  Traveling Salesman Problem , 2016 .

[5]  Andrew Wolfe,et al.  Compilation techniques for low energy: an overview , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[6]  Chi-Ying Tsui,et al.  Low power architecture design and compilation techniques for high-performance processors , 1994, Proceedings of COMPCON '94.

[7]  Hiroyuki Tomiyama,et al.  Instruction Schecduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches (Special Section on VLSI Design and CAD Algorithms) , 1998 .

[8]  Sharad Malik,et al.  Instruction level power analysis and optimization of software , 1996, Proceedings of 9th International Conference on VLSI Design.

[9]  Santosh Pande,et al.  Code Restructuring for Improving Real Time Response through Code Speed, Size Trade-offs on Limited Memory Embedded DSPs , 1999, LCPC.

[10]  Mark C. Johnson,et al.  Software design for low power , 1997 .

[11]  Thomas D. Burd,et al.  Energy efficient CMOS microprocessor design , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[12]  Niraj K. Jha,et al.  Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Jenq Kuen Lee,et al.  Compiler optimization on instruction scheduling for low power , 2000, ISSS '00.

[14]  R. Prim.  Shortest connection networks and some generalizations , 1957 .

[15]  Kailash C. Kapur,et al.  Reliability in engineering design , 1977 .