An Integrated Approach to Optimize Power Device Performances by Means of Stress Engineering

In the present work it is shown how stress engineering can be used in semiconductor industry to improve Power MOSFET transistor’s performance beyond simple geometrical downscaling. The aim of this paper is to present an integrated methodology, coupling modelling and experimental results, focused on the structural optimization of a power device by means of final passivation mechanical stress tuning. The proposed approach is based on a Finite Element Model that describes and predicts the mechanical strain of a singulated power device (MOSFET) validated by the correlation with interferometric experimental warpage measurements (Topography and Deformation Measurements). Scope of the activity is to engineer Power Devices with reduced intrinsic stresses in order to optimize the reliability performances. Controlled stress into a single semiconductor crystal oriented substrate can be managed at manufacturing level by several methods, including the introduction of a layer on the top of the substrate or around the gate region. From the knowledge of the mechanical boundaries, as a function of temperature, it is possible to predict the stress conditions impacting on device fabrication and on reliability performances. Moreover, according to the piezoresistive model, it has been evaluated the electrical characteristics (on-resistance) in the operative working condition range. According to the proposed approach an optimized passivation layer solution has been proposed, simulated by Finite Element model and validated by experiments.

[1]  Piezomobility description of strain-induced mobility , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[2]  K. Yahashi,et al.  High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique , 2006, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[3]  Alessandro Sitta,et al.  Fast transient thermomechanical stress to set a pressure-assisted sintering process , 2019, 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME).

[4]  E. Suhir.  Analysis of interfacial thermal stresses in a trimaterial assembly , 2001 .

[5]  Domenico Guida,et al.  Finite element analysis on squeal-noise in railway applications , 2018 .

[6]  M. Oliveri,et al.  Mechanical properties of amorphous Ge2Sb2Te5 thin layers , 2018, Surface and Coatings Technology.

[7]  L. Luo,et al.  Influence of observed anelasticity of Cu on the wafer warpage evolution during thermal processes , 2018, 2018 19th International Conference on Electronic Packaging Technology (ICEPT).

[8]  Klaus-Dieter Lang,et al.  Dependency of the porosity and the layer thickness on the reliability of Ag sintered joints during active power cycling , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[9]  Michele Calabretta,et al.  Mechanical and electrical characterization of CVD-grown graphene transferred on chalcogenide Ge2Sb2Te5 layers , 2018, Carbon.

[10]  Frede Blaabjerg,et al.  Prediction of bond wire fatigue of IGBTs in a PV inverter under long-term operation , 2016, 2015 IEEE Applied Power Electronics Conference and Exposition (APEC).

[11]  Ahmed A. Shabana,et al.  A New Ancf/CRBF Fully Parameterized Plate Finite Element , 2017 .

[12]  L. Luo,et al.  Deep Understanding the role of Cu in RDL to Warpage by Exploring the Warpage Evolution with Microstructural Changes , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[13]  Gaetano Bazzano,et al.  Thermal Analysis Approach for Predicting Power Device Lifetime , 2019, IEEE Transactions on Device and Materials Reliability.

[14]  C.-Y. Yu,et al.  Mobility-enhancement technologies , 2005, IEEE Circuits and Devices Magazine.

[15]  Michele Calabretta,et al.  Solder Joint Reliability: Thermo-mechanical analysis on Power Flat Packages , 2017 .

[16]  Y. Kanda,et al.  A graphical representation of the piezoresistance coefficients in silicon , 1982, IEEE Transactions on Electron Devices.

[17]  Aditi Mallik,et al.  Simulation of Process-Stress Induced Warpage of Silicon Wafers Using ANSYS® Finite Element Analysis , 2010 .

[18]  S. Thompson,et al.  Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High ($\sim$1.5 GPa) Channel Stress , 2007, IEEE Electron Device Letters.

[19]  W. Johnson,et al.  On multi-metal thermostats , 1961 .

[20]  Giuseppe Greco,et al.  Numerical approach to predict power device reliability , 2018, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

[21]  W. Van Paepegem,et al.  Application of digital phase-shift shadow Moiré to micro deformation measurements of curved surfaces , 2001 .

[22]  D. Weidmann,et al.  Determination of strength of interface in packages based on an approach using coupling of experimental and modeling results , 2011, 2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems.