Temperature cycling analysis for ball grid array package using finite element analysis
暂无分享,去创建一个
Ghulam Abdul Quadir | Muhammad Nubli Zulkifli | M. Zulkifli | Zul Azhar Zahid Jamal | Z. Jamal | G. A. Quadir
[1] Guna S Selvaduray,et al. Solder joint fatigue models: review and applicability to chip scale packages , 2000 .
[2] B. A. Zahn. Impact of ball via configurations on solder joint reliability in tape-based, chip-scale packages , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).
[3] J. Van de Peer,et al. Probabilistic design approach for package design and solder joint reliability optimization for a lead free BGA package , 2005, EuroSimE 2005. Proceedings of the 6th International Conference on Thermal, Mechanial and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2005..
[4] Sidharth,et al. Board level solder reliability vs. ramp rate & dwell time during temperature cycling , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[5] Robert Darveaux,et al. Effect of Simulation Methodology on Solder Joint Crack Growth Correlation and Fatigue Life Prediction , 2002 .
[6] G. Q. Zhang,et al. Parametric study on flip chip package with lead-free solder joints by using the probabilistic designing approach , 2004, Microelectron. Reliab..
[7] L. Zhang,et al. Response surface models for efficient, modular estimation of solder joint reliability in area array packages , 2005, Microelectron. Reliab..
[8] Bart Vandevelde,et al. Parameterized Modeling of Thermomechanical Reliability for CSP Assemblies , 2003 .
[9] Stefan Reh,et al. Probabilistic finite element analysis using ANSYS , 2006 .
[10] Wei Ren,et al. A simulation-based multi-objective design optimization of electronic packages under thermal cycling and bending , 2004, Microelectron. Reliab..
[11] Yi-Shao Lai,et al. Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages , 2007, Microelectron. Reliab..
[12] W.D. van Driel,et al. Design for Reliability of Wafer Level Packages , 2006, EuroSime 2006 - 7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems.
[13] D. Agonafer,et al. Design optimization and reliability of PWB level electronic package , 2004, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543).
[14] Enrique Del Castillo,et al. Process Optimization: A Statistical Approach , 2007 .
[15] L. Anand. Constitutive equations for hot-working of metals , 1985 .
[16] R. Darveaux. Effect of simulation methodology on solder joint crack growth correlation , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
[17] Chang-Chun Lee,et al. Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology , 2007, Microelectron. Reliab..
[18] Rong-Sheng Chen,et al. Packaging parameter analysis and optimization design on solder joint reliability for twin die stacked packages by variance in strain energy density (SED) of each solder joint , 2008, Microelectron. Reliab..