CORDIC-based high-speed direct digital frequency synthesis

and patience he rendered throughout my graduate study at the University of Texas at Austin.

[1]  Wonyong Sung,et al.  VLSI design of a CORDIC-based derotator , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[2]  Wonyong Sung,et al.  A fast direction sequence generation method for CORDIC processors , 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[3]  Venceslav F. Kroupa.  Methods of Mapping from Phase to Sine Amplitude in Direct Digital Synthesis , 1999 .

[4]  Edgar Sanchez-Sinencio,et al.  A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer , 2002, IEEE J. Solid State Circuits.

[5]  Jeong-A Lee,et al.  Constant-Factor Redundant CORDIC for Angle Calculation and Rotation , 1992, IEEE Trans. Computers.

[6]  Tobias G. Noll.  Carry-save architectures for high-speed digital signal processing , 1991, J. VLSI Signal Process..

[7]  H. Samueli,et al.  A 700-MHz 24-b pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator , 1993 .

[8]  Jack Sklansky,et al.  Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..

[9]  Hassan M. Ahmed,et al.  Efficient elementary function generation with multipliers , 1989, Proceedings of 9th Symposium on Computer Arithmetic.

[10]  D.E. Atkins.  Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods , 1970, IEEE Transactions on Computers.

[11]  Michael J. Flanagan,et al.  Spur-reduced digital sinusoid synthesis , 1993, IEEE Trans. Commun..

[12]  A. Torosyan,et al.  A 300 MHz quadrature direct digital synthesizer/mixer in 0.25 /spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[13]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[14]  R. F. Shaw.  Arithmetic Operations in a Binary Computer , 1950 .

[15]  Heinrich Meyr,et al.  VLSI implementation of the CORDIC algorithm using redundant arithmetic , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[16]  J. S. Walther,et al.  A unified algorithm for elementary functions , 1899, AFIPS '71 (Spring).

[17]  D. De Caro,et al.  Direct digital frequency synthesizers using high-order polynomial approximation , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[18]  John G. Proakis,et al.  Probability, random variables and stochastic processes , 1985, IEEE Trans. Acoust. Speech Signal Process..

[19]  B. Gold,et al.  A digital frequency synthesizer , 1971 .

[20]  Shuzo Yajima,et al.  Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation , 1991, IEEE Trans. Computers.

[21]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[22]  C. Chien,et al.  Computer-aided design of a BPSK spread-spectrum chip set , 1992 .

[23]  Behrooz Parhami,et al.  Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations , 1990, IEEE Trans. Computers.

[24]  A. Y. Kwentus,et al.  A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range , 1999, IEEE J. Solid State Circuits.

[25]  Douglas Stott Parker,et al.  Analysis of Rounding Methods in Floating-Point Arithmetic , 1977, IEEE Transactions on Computers.

[26]  Venceslav F. Kroupa,et al.  A 200 MHz Quadrature Digital Synthesizer/Mixer in 0.8 m CMOS , 1999 .

[27]  Earl E. Swartzlander,et al.  An analysis of the CORDIC algorithm for direct digital frequency synthesis , 2002, Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors.

[28]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[29]  Tomás Lang,et al.  Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD , 1990, IEEE Trans. Computers.

[30]  W. A. Chren.  RNS-based enhancements for direct digital frequency synthesis , 1995 .

[31]  Daniel E. Atkins,et al.  Introduction to the Role of Redundancy in Computer Arithmetic , 1975, Computer.

[32]  Vincenzo Piuri,et al.  Pipelined Adders , 1996, IEEE Trans. Computers.

[33]  Dirk Timmermann,et al.  Low Latency Time CORDIC Algorithms , 1992, IEEE Trans. Computers.

[34]  Kiseon Kim,et al.  A digital sinusoid synthesis based on the postscaled CORDIC , 1999, Fifth Asia-Pacific Conference on ... and Fourth Optoelectronics and Communications Conference on Communications,.

[35]  Alan V. Oppenheim,et al.  Discrete-time Signal Processing. Vol.2 , 2001 .

[36]  Heinrich Meyr,et al.  The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations , 1996, IEEE Trans. Computers.

[37]  Kari Halonen,et al.  A direct digital synthesizer with an on-chip D/A-converter , 1997 .

[38]  James E. Robertson,et al.  Logical design of a redundant binary adder , 1978, 1978 IEEE 4th Symposium onomputer Arithmetic (ARITH).

[39]  Earl E. Swartzlander,et al.  Hybrid CORDIC Algorithms , 1997, IEEE Trans. Computers.

[40]  Yu Hen Hu,et al.  The quantization effects of the CORDIC algorithm , 1992, IEEE Trans. Signal Process..

[41]  H. Samueli,et al.  The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects , 1988, Proceedings of the 42nd Annual Frequency Control Symposium, 1988..

[42]  Y.H. Hu,et al.  CORDIC-based VLSI architectures for digital signal processing , 1992, IEEE Signal Processing Magazine.

[43]  R. J. van de Plassche,et al.  A 540-MHz 10-b polar-to-Cartesian converter , 1991 .

[44]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[45]  H. Samueli,et al.  A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance , 1991 .

[46]  B. Daneshrad,et al.  Direct digital frequency synthesis using a modified CORDIC , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).