Reversible Comparator Circuit Design using CMOS-GDI-TG Mixed Technology

In this paper we design GDI, TG and GDI-TG Mixed based Reversible Comparator circuit (3) using 90 nm & 180nm Technology. Reversible gates using transistors has been designed using a combination of CMOS-GDI-TG circuit, which provides the optimal solution for combinational logic, saving 1/3 the power, half the area and 10% in delay relative to a CMOS implementation (7). In this paper different circuits using different technologies are implemented.

[1]  Chi-Ying Tsui,et al.  High-performance single clock cycle CMOS comparator , 2006 .

[2]  Hoi-Jun Yoo,et al.  Bitwise Competition Logic for compact digital comparator , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[3]  Parag K. Lala,et al.  Reversible-logic design with online testability , 2006, IEEE Transactions on Instrumentation and Measurement.

[4]  Chi-Ying Tsui,et al.  A mux-based High-Performance Single-Cycle CMOS Comparator , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Marco Lanuzza,et al.  A new low-power high-speed single-clock-cycle binary comparator , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[6]  Wenjuan Li,et al.  Using new designed NLG gate for the realization of four-bit reversible numerical comparator , 2010, 2010 International Conference on Educational and Network Technology.

[7]  Chung-Hsun Huang,et al.  High-performance and power-efficient CMOS comparators , 2003 .