Robust design of high fan-in/out subthreshold circuits

Operating CMOS circuits with power supplies below the threshold voltage has been suggested for ultra-low power systems. High fan-in or fan-out circuits, such as those in memories, are prone to failure when operating in this regime. Vanishing noise margins due to reduced transistor on-to-off current ratios result in circuit failure as the supply voltage shrinks. Therefore, design guidelines for robust subthreshold logic circuit are developed in this paper. First, an analytical model is derived to determine a circuit's fan-in/out limitations and the minimum supply voltage for robust subthreshold operation. Excellent agreement between the analytical model and circuit simulations is shown. This model is applied to the analysis of circuit robustness as affected by design choices, both systematic and random processing variations, supply voltage fluctuations, and temperature variations.

[1]  Anantha Chandrakasan,et al.  Optimal supply and threshold scaling for subthreshold CMOS circuits , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[2]  David Blaauw,et al.  Theoretical and practical limits of dynamic voltage scaling , 2004, Proceedings. 41st Design Automation Conference, 2004..

[3]  L. Geddes,et al.  Historical highlights in cardiac pacing , 1990, IEEE Engineering in Medicine and Biology Magazine.

[4]  A. Chandrakasan,et al.  A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.

[5]  Alex Pentland,et al.  The digital doctor: an experiment in wearable telemedicine , 1997, Digest of Papers. First International Symposium on Wearable Computers.

[6]  Sterling R. Whitaker,et al.  Low power radiation tolerant VLSI for advanced spacecraft , 2002, Proceedings, IEEE Aerospace Conference.

[7]  Thad Starner,et al.  Human-Powered Wearable Computing , 1996, IBM Syst. J..

[8]  Anantha Chandrakasan,et al.  Characterizing and modeling minimum energy operation for subthreshold circuits , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[9]  Kaushik Roy,et al.  Robust subthreshold logic for ultra-low power operation , 2001, IEEE Trans. Very Large Scale Integr. Syst..