Programmable restricted SEC codes to mask permanent faults in semiconductor memories

With increasing storage capacities, spare memory columns aimed at replacing defective regular columns remain generally available to repair malfunctioning storage cells. The existing repair methods are based on column replacement. Consequently, the number of single-bit hard errors induced by malfunctioning storage cells is linear with respect to the number of redundant columns. We propose restricted single-error correction (RSEC) codes to enable the correction of an exponential number of single-bit errors. The RSEC codes are characterized by programmable parity-check matrices which allow the correction of different sets of errors. Depending on the accessed memory bank or segment, these matrices can be generated out of the (built-in) test result bits which indicate the columns with defective storage cells. The resulting RSEC-based method improves the memory repair capacity with limited performance overhead. Memory protection schemes are proposed in which each redundant column is used either to store RSEC check-bits or to replace completely defective regular columns.

[1]  M. Nicolaidis,et al.  Dynamic Data-bit Memory Built-In Self- Repair , 2003, ICCAD 2003.

[2]  Lorena Anghel,et al.  A diversified memory built-in self-repair approach for nanotechnologies , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[3]  Frederic T. Chong,et al.  A pageable, defect-tolerant nanoscale memory system , 2007, 2007 IEEE International Symposium on Nanoscale Architectures.

[4]  Chin-Long Chen,et al.  Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..

[5]  Shekhar Y. Borkar,et al.  Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.

[6]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[7]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.

[8]  Charles H. Stapper,et al.  Synergistic Fault-Tolerance for Memory Chips , 1992, IEEE Trans. Computers.

[9]  Jin-Fu Li,et al.  A built-in self-repair design for RAMs with 2-D redundancy , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  R. Harboe-Sorensen,et al.  Can Atmospheric Neutrons Induce Soft Errors in nand Floating Gate Memories? , 2009, IEEE Electron Device Letters.

[11]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[12]  Tom Chen,et al.  An ultra-large capacity single-chip memory architecture with self-testing and self-repairing , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[13]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[14]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[15]  Nur A. Touba,et al.  Exploiting Unused Spare Columns to Improve Memory ECC , 2009, 2009 27th IEEE VLSI Test Symposium.

[16]  S. E. Schuster.  Multiple word/bit line redundancy for semiconductor memories , 1978 .

[17]  Timothy J. Dell,et al.  A white paper on the benefits of chipkill-correct ecc for pc server main memory , 1997 .

[18]  M. Horiguchi,et al.  Redundancy techniques for high-density DRAMs , 1997, 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon.

[19]  Shu Lin,et al.  Error control coding : fundamentals and applications , 1983 .