Comparative analysis of adiabatic logic styles

Over the past decade, different adiabatic logic styles for low-power applications have been published. This paper compares and analyzes the performance and energy dissipation of various adiabatic logic styles in a uniform test environment. The test benches are laid out and a test chip has been fabricated in a standard 0.18 /spl mu/m CMOS technology. The results are mainly based on test chip measurements and post layout simulations.

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