Generation of Distributed Loop Control

We present a new methodology for controlling the space-time behavior of VLSI and FPGA-based processor arrays. The main idea is to generate simple local control elements which take control over the activeness of each attached processor element. Each control element thereby propagates a "start" and a "stop execution" signal to its neighbors. We show that our control mechanism is much more efficient than existing approaches because 1) only two control signals (start/stop) are required, 2) no extension of the computation space is necessary. 3) By the local propagation of just one start/stop signal, energy is saved as processing elements are only active between the time they have received the start signal and the time they have received the stop signal. Our methodology is applicable to one- and multi-dimensional processor arrays and is based on local control signal propagation. We provide a theoretical analysis of the overhead caused by the control structure.

[1]  E. Ehrhart,et al.  Polynômes arithmétiques et méthode des polyèdres en combinatoire , 1974 .

[2]  David K. Smith Theory of Linear and Integer Programming , 1987 .

[3]  Lothar Thiele,et al.  Resource constrained scheduling of uniform algorithms , 1993, J. VLSI Signal Process..

[4]  Jingling Xue Formal synthesis of control signals for systolic arrays , 1992 .

[5]  Vincent Loechner,et al.  Parametric Analysis of Polyhedral Iteration Spaces , 1998, J. VLSI Signal Process..

[6]  D.I. Moldovan,et al.  On the design of algorithms for VLSI systolic arrays , 1983, Proceedings of the IEEE.

[7]  Jürgen Teich,et al.  Design Space Exploration for Massively Parallel Processor Arrays , 2001, PaCT.

[8]  Jürgen Teich,et al.  Partitioning of processor arrays: a piecewise regular approach , 1993, Integr..

[9]  Jürgen Teich,et al.  Synthesis of FPGA Implementations from Loop Algorithms , 2001 .

[10]  Yves Robert,et al.  Linear Scheduling Is Nearly Optimal , 1991, Parallel Process. Lett..

[11]  Lothar Thiele,et al.  On the design of piecewise regular processor arrays , 1989, IEEE International Symposium on Circuits and Systems,.

[12]  Jürgen Teich,et al.  Control generation in the design of processor arrays , 1991, J. VLSI Signal Process..

[13]  Richard M. Karp,et al.  The Organization of Computations for Uniform Recurrence Equations , 1967, JACM.

[14]  E. Wagner International Series of Numerical Mathematics , 1963 .

[15]  Christian Lengauer,et al.  Loop Parallelization in the Polytope Model , 1993, CONCUR.

[16]  Michael Wolfe,et al.  High performance compilers for parallel computing , 1995 .

[17]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[18]  Jürgen Teich A compiler for application specific processor arrays , 1993 .