Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex.

[1]  H. Markram.  The Blue Brain Project , 2006, Nature Reviews Neuroscience.

[2]  Paul E. Hasler,et al.  Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit , 2013, Neural Networks.

[3]  T. Chan,et al.  A true single-transistor oxide-nitride-oxide EEPROM device , 1987, IEEE Electron Device Letters.

[4]  Willy M. C. Sansen,et al.  Low-noise wide-band amplifiers in bipolar and CMOS technologies , 1990, The Kluwer international series in engineering and computer science.

[5]  André van Schaik,et al.  Stochastic Electronics: A Neuro-Inspired Design Paradigm for Integrated Circuits , 2014, Proceedings of the IEEE.

[6]  Sylvie Renaud,et al.  A $Q$ -Modification Neuroadaptive Control Architecture for Discrete-Time Systems , 2010 .

[7]  Mostafa Rahimi Azghadi,et al.  Spike-Based Synaptic Plasticity in Silicon: Design, Implementation, Application, and Challenges , 2014, Proceedings of the IEEE.

[8]  J. Assad,et al.  Beyond Poisson: Increased Spike-Time Regularity across Primate Parietal Cortex , 2009, Neuron.

[9]  Sylvie Renaud,et al.  Real-Time Simulation of Biologically Realistic Stochastic Neurons in VLSI , 2010, IEEE Transactions on Neural Networks.

[10]  Bartlett W. Mel,et al.  Computational subunits in thin dendrites of pyramidal cells , 2004, Nature Neuroscience.

[11]  Trevor Bekolay,et al.  A Large-Scale Model of the Functioning Brain , 2012, Science.

[12]  Yong-Bin Kim,et al.  Low power real time electronic neuron VLSI design using subthreshold technique , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[13]  René Schüffny,et al.  Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS , 2014, Front. Neurosci..

[14]  Gert Cauwenberghs,et al.  Neuromorphic Silicon Neuron Circuits , 2011, Front. Neurosci.

[15]  C. Hu,et al.  BSIM4 gate leakage model including source-drain partition , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[16]  Giacomo Indiveri,et al.  A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses , 2015, Front. Neurosci..

[17]  Sang Woon Lee,et al.  Capacitors with an Equivalent Oxide Thickness of <0.5 nm for Nanoscale Electronic Semiconductor Memory , 2010 .

[18]  J.V. Arthur,et al.  Recurrently connected silicon neurons with active dendrites for one-shot learning , 2004 .

[19]  C. Diorio,et al.  A simulation model for floating-gate MOS synapse transistors , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[20]  A. Hodgkin,et al.  A quantitative description of membrane current and its application to conduction and excitation in nerve , 1952, The Journal of physiology.

[21]  Carver A. Mead,et al.  Neuromorphic electronic systems , 1990, Proc. IEEE.

[22]  Giacomo Indiveri,et al.  A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity , 2006, IEEE Transactions on Neural Networks.

[23]  Anthony N. Burkitt,et al.  A Review of the Integrate-and-fire Neuron Model: I. Homogeneous Synaptic Input , 2006, Biological Cybernetics.

[24]  D. Frank,et al.  Reduction of random telegraph noise in High-к / metal-gate stacks for 22 nm generation FETs , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[25]  Paul Hasler,et al.  A family of floating-gate adapting synapses based upon transistor channel models , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[26]  Chenming Hu,et al.  High endurance ultra-thin tunnel oxide for dynamic memory application , 1995, Proceedings of International Electron Devices Meeting.

[27]  C. Hu,et al.  Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling , 2001 .

[28]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .

[29]  Craig T. Jin,et al.  A log-domain implementation of the Izhikevich neuron model , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[30]  Michael J. Uren,et al.  1/f and random telegraph noise in silicon metal‐oxide‐semiconductor field‐effect transistors , 1985 .

[31]  Andrew S. Cassidy,et al.  A million spiking-neuron integrated circuit with a scalable communication network and interface , 2014, Science.

[32]  D. Schroeder,et al.  MemFlash device: floating gate transistors as memristive devices for neuromorphic computing , 2014 .

[33]  W. Wildman,et al.  Theoretical Neuroscience , 2014 .

[34]  Wulfram Gerstner,et al.  SPIKING NEURON MODELS Single Neurons , Populations , Plasticity , 2002 .

[35]  H. Nyquist.  Thermal Agitation of Electric Charge in Conductors , 1928 .

[36]  Paul Hasler,et al.  Floating-gate MOS synapse transistors , 1998 .

[37]  Paul E. Hasler,et al.  Single Transistor Learning Synapses , 1994, NIPS.

[38]  P.K. Ko,et al.  Random telegraph noise of deep-submicrometer MOSFETs , 1990, IEEE Electron Device Letters.

[39]  Chih-Hung Chen,et al.  A review of gate tunneling current in MOS devices , 2006, Microelectron. Reliab..

[40]  Doo Seok Jeong,et al.  Reliability of neuronal information conveyed by unreliable neuristor-based leaky integrate-and-fire neurons: a model study , 2015, Scientific Reports.

[41]  M. Kobayashi,et al.  Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs , 2012, 2012 International Electron Devices Meeting.

[42]  Chris Eliasmith,et al.  Neural Engineering: Computation, Representation, and Dynamics in Neurobiological Systems , 2004, IEEE Transactions on Neural Networks.

[43]  Doo Seok Jeong,et al.  Tunneling current from a metal electrode to many traps in an insulator , 2005 .

[44]  Piotr Dudek,et al.  Compact silicon neuron circuit with spiking and bursting behaviour , 2008, Neural Networks.

[45]  Gert Cauwenberghs,et al.  Synthesis of Log-Domain Filters from First-Order Building Blocks , 2000 .

[46]  D. Jeong,et al.  Giant electrode effect on tunnelling electroresistance in ferroelectric tunnel junctions , 2014, Nature Communications.

[47]  R. Kuroda,et al.  The study of time constant analysis in random telegraph noise at the subthreshold voltage region , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[48]  C. Mead,et al.  White noise in MOS transistors and resistors , 1993, IEEE Circuits and Devices Magazine.

[49]  A. Visconti,et al.  Flash memory reliability , 2005, 2005 IEEE International Integrated Reliability Workshop.

[50]  Eugene M. Izhikevich,et al.  Simple model of spiking neurons , 2003, IEEE Trans. Neural Networks.

[51]  Kwabena Boahen,et al.  Synchrony in Silicon: The Gamma Rhythm , 2007, IEEE Transactions on Neural Networks.

[52]  J. Brant Arseneau,et al.  VLSI and neural systems , 1990 .

[53]  J.P. Campbell,et al.  Random telegraph noise in highly scaled nMOSFETs , 2009, 2009 IEEE International Reliability Physics Symposium.

[54]  C. Hu,et al.  Random telegraph noise in flash memories - model and technology scaling , 2007, 2007 IEEE International Electron Devices Meeting.

[55]  Chiara Bartolozzi,et al.  Synaptic Dynamics in Analog VLSI , 2007, Neural Computation.

[56]  Jennifer Hasler,et al.  Neuron Array With Plastic Synapses and Programmable Dendrites , 2013, IEEE Transactions on Biomedical Circuits and Systems.

[57]  K. H. Britten,et al.  Power spectrum analysis of bursting cells in area MT in the behaving monkey , 1994, The Journal of neuroscience : the official journal of the Society for Neuroscience.

[58]  Doo Seok Jeong,et al.  Towards artificial neurons and synapses: a materials point of view , 2013 .

[59]  R. Douglas,et al.  A silicon neuron , 1991, Nature.

[60]  D. Jeong,et al.  Emerging memories: resistive switching mechanisms and current status , 2012, Reports on progress in physics. Physical Society.

[61]  Gert Cauwenberghs,et al.  A floating-gate programmable array of silicon neurons for central pattern generating networks , 2006, 2006 IEEE International Symposium on Circuits and Systems.