Modeling Thermal Effects in Nanodevices

In order to investigate the role of self-heating effects on the electrical characteristics of nanoscale devices, we implemented a 2D Monte Carlo device simulator that includes the self-consistent solution of the energy balance equations for both acoustic and optical phonons. The acoustic and optical phonon temperatures are fed back into the electron transport solver through temperature-dependent scattering tables. The electrothermal device simulator was used in the study of different generations of nanoscale fully depleted silicon-on-insulator devices that are either already in production or will be fabricated in the next five to ten years. We find less degradation due to self-heating in very short channel device structures due to the increasing role of nonstationary velocity-overshoot effects which are less sensitive to the local temperature.

[1]  S. Goodnick,et al.  Nonequilibrium longitudinal-optical phonon effects in GaAs-AlGaAs quantum wells. , 1987, Physical review letters.

[2]  C. Cercignani.  The Boltzmann equation and its applications , 1988 .

[3]  P. Lugli,et al.  III.1 – Hot-Carrier Relaxation in Quasi-2D Systems , 1992 .

[4]  A. Majumdar,et al.  Concurrent thermal and electrical modeling of sub‐micrometer silicon devices , 1996 .

[5]  D. Schroder,et al.  Scaled silicon MOSFETs: degradation of the total gate capacitance , 1997 .

[6]  M. A. Alam,et al.  Effects of carrier heating on laser dynamics-a Monte Carlo study , 1997 .

[7]  A. Majumdar,et al.  Microscale energy transport , 1998 .

[8]  THE INFLUENCE OF SPACE QUANTIZATION EFFECTS ON THE THRESHOLD VOLTAGE, INVERSION LAYER AND TOTAL GATE CAPACITANCES IN SCALED SI-MOSFETS , 1999 .

[9]  E. Pop,et al.  Localized heating effects and scaling of sub-0.18 micron CMOS devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[10]  Ali Shakouri,et al.  Heat Transfer in Nanostructures for Solid-State Energy Conversion , 2002 .

[11]  S. Datta,et al.  Silicon nano-transistors and breaking the 10 nm physical gate length barrier , 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

[12]  Ashok Raman,et al.  Simulation of nonequilibrium thermal effects in power LDMOS transistors , 2003 .

[13]  Cristina H. Amon,et al.  Submicron heat transport model in silicon accounting for phonon dispersion and polarization , 2004 .

[14]  Shinichi Takagi,et al.  Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs , 2004 .

[15]  D. Vasileska,et al.  Narrow-width SOI devices: the role of quantum-mechanical size quantization effect and unintentional doping on the device operation , 2005, IEEE Transactions on Electron Devices.

[16]  E. Pop,et al.  Non-Equilibrium Phonon Distributions in Sub-100nm Silicon Transistors , 2006 .

[17]  The role of the temperature boundary conditions on the gate electrode on the heat distribution in 25 nm FD-SOI MOSFETs with SiO2 and gate-stack (High-K Dielectric) as the gate oxide , 2007, 2007 International Semiconductor Device Research Symposium.

[18]  T. Sadi,et al.  Electrothermal Monte Carlo Simulation of Submicrometer Si/SiGe MODFETs , 2007, IEEE Transactions on Electron Devices.

[19]  Electrothermal Monte Carlo simulation of submicron wurtzite GaN/AlGaN HEMTs , 2007 .

[20]  Modeling thermal effects in nano-devices , 2008 .