Area-efficient layout design for output transistors with consideration of ESD reliability

A novel hexagon-type layout is proposed to realize large-dimension CMOS output transistors with smaller layout area but higher ESD reliability. The drain parasitic capacitance of hexagon-type layout is also smaller than that of traditional finger-type layout. Experimental results have shown that the maximum driving capability per layout area of output transistor with hexagon-type layout is improved 30% more than that with finger-type layout. This hexagon-type layout is very suitable for deep-submicron low-voltage CMOS ICs in high-density applications.