A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

The two-dimensional discrete cosine transform (2D DCT) has been widely recognized as a key processing unit for image data compression/decompression. In this paper, the implementation of a 200 MHz 13.3 mm/sup 2/ 8/spl times/8 2-D DCT macrocell capable of HDTV rates, based on a direct realization of the DCT, and using distributed arithmetic is presented. The macrocell, fabricated using 0.8 /spl mu/m base-rule CMOS technology and 0.5 /spl mu/m MOSFET's, performs the DCT processing with 1 sample-(pixel)-per-clock throughput. The fast speed and small area are achieved by a novel sense-amplifying pipeline flip-flop (SA-F/F) circuit technique in combination with nMOS differential logic. The SA-F/F, a class of delay flip-flops, can be used as a differential synchronous sense-amplifier, and can amplify dual-rail inputs with swings lower than 100 mV. A 1.6 ns 20 bit carry skip adder used in the DCT macrocell, which was designed by the same scheme, is also described. The adder is 50% faster and 30% smaller than a conventional CMOS carry look ahead adder, which reduces the macrocell size by 15% compared to a conventional CMOS implementation. >

[1]  C.A.T. Salama,et al.  CMOS differential pass-transistor logic design , 1987 .

[2]  Trevor York,et al.  Book Review: Principles of CMOS VLSI Design: A Systems Perspective , 1986 .

[3]  Didier Le Gall,et al.  MPEG: a video compression standard for multimedia applications , 1991, CACM.

[4]  C.A.T. Salama,et al.  Design of submicrometer CMOS differential pass-transistor logic circuits , 1991 .

[5]  Lee-Sup Kim,et al.  200 MHz video compression macrocells using low-swing differential logic , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[6]  Y. Inoue,et al.  A 100MHz 2-D Discrete Cosine Transform Core Processor , 1991, Symposium on VLSI Circuits.

[7]  Yukihiro Fujimoto,et al.  A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture , 1993 .

[8]  Kazuo Yano,et al.  A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic , 1990 .

[9]  Ming Lei Liou,et al.  Overview of the p×64 kbit/s video coding standard , 1991, CACM.

[10]  Gregory K. Wallace,et al.  The JPEG still picture compression standard , 1991, CACM.

[11]  Masahiko Yoshimoto,et al.  A 100-MHz 2-D discrete cosine transform core processor , 1992 .

[12]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[13]  Kenji Maeguchi,et al.  A single-chip MPEG2 video decoder LSI , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[14]  G. Goto,et al.  An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit , 1992 .

[15]  Wen-Hsiung Chen,et al.  A Fast Computational Algorithm for the Discrete Cosine Transform , 1977, IEEE Trans. Commun..

[16]  Ting Chen,et al.  VLSI implementation of a 16*16 discrete cosine transform , 1989 .