An effective BIST architecture for sequential fault testing in array multipliers

Sequential fault testing approaches for array multipliers proposed in the past target only external testing and impose significant hardware overhead due to excessive DFT modifications. In this paper we present, for the first time, a BIST architecture which does not require any DFT modifications in the multiplier structure and provides a fault coverage larger than 99% for a comprehensive sequential fault model (RS-CFM) for any multiplier size. Both robust and non-robust testing are considered. The applicability of the BIST architecture is further justified considering the case of the transistor stuck-open fault model, where a fault coverage larger than 99% is also achieved in any case.

[1]  Janusz Rajski,et al.  Test responses compaction in accumulators with rotate carry adders , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[3]  Spyros Tragoudas,et al.  ATPD: an automatic test pattern generator for path delay faults , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[4]  Shyue-Kung Lu,et al.  Cell delay fault testing for iterative logic arrays , 1996, J. Electron. Test..

[5]  Dimitris Gizopoulos,et al.  Testing CMOS combinational iterative logic arrays for realistic faults , 1996, Integr..

[6]  Niraj K. Jha,et al.  Testing and Reliable Design of CMOS Circuits , 1989 .

[7]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[8]  Mihalis Psarakis,et al.  Robust sequential fault testing of iterative logic arrays , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[9]  M.H. Woods,et al.  MOS VLSI reliability and yield trends , 1986, Proceedings of the IEEE.

[10]  Yervant Zorian,et al.  Robustly testable array multipliers under realistic sequential cell fault model , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[11]  Charles R. Kime,et al.  Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults , 1985, International Test Conference.

[12]  Vishwani D. Agrawal,et al.  Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[13]  F. Joel Ferguson,et al.  Oscillation and sequential behavior caused by interconnect opens in digital CMOS circuits , 1997, Proceedings International Test Conference 1997.

[14]  Sudhakar M. Reddy,et al.  On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[15]  Cheng-Wen Wu,et al.  Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns , 1994, IEEE Trans. Computers.

[16]  Yervant Zorian,et al.  An Effective Built-In Self-Test Scheme for Parallel Multipliers , 1999, IEEE Trans. Computers.