Applying Optical Interconnects to the 3-D Computer: A Performance Evaluation

Two methods for fault diagnosis on a class of rearrangeable networks using the same fault model for blocking multistage networks are developed. The first method uses minimal two-bit test vectors and uniform switch settings in two phases to detect and locate a fault. In most cases, the number of tests needed is independent of the network size. The second method uses (n + 1)-bit test vectors and nonuniform switch settings in two test phases. Speedup of the process is obtained in many cases. Again, the number of tests needed is independent of the network size in most cases. A combination of these two methods is proposed to achieve greater efficiency.