VCO를 이용한 5㎒ 대역폭, 8bit 해상도를 갖는 High-speed Delta-Sigma Modulator

Reduced power supply voltages, lower device intrinsic gain, and increased flicker noise in scaled CMOS technologies present challenges in designing analog circuits, especially op-amps, so many papers published recently describe various techniques to substitute op-amps with other easy-to-design circuits in deep-submicron technologies. This paper introduces an approach to realizing a VCO-based integrator and a VCO-based delta-sigma modulator, thus removing op-amps. The proposed technique is more amenable to design in scaled technologies, and post-layout simulation demonstrates that the implemented ADC has a peak SNR of 50㏈ and the core consumes 2.1㎃ from a 1.8V supply.