Settable and resettable D trigger resisting single event upset

The present invention discloses an anti SEU can be set and reset D flip-flops, the purpose is to improve the set and reset of the D flip-flops single event flip anti SEU capability. It consists of a clock circuit, a buffer circuit is reset, the master latch and the slave latch output buffer circuit; master latch by a fourteen fourteen PMOS transistor and NMOS tube composed of, from the PMOS latch of ten NMOS tube and ten tubes, the master latch and the slave latch reinforcement redundant dual-mode were carried out, and the master latch and the slave latch improved C2MOS the circuit, i.e. the separation of the mutually redundant C2MOS circuit pullup and pulldown NMOS transistor PMOS transistor. The present invention is an anti-single event SEU can set and reset the D flip-flip strong ability for standard cell libraries used against SEU reinforcement integrated circuit, used in aviation and aerospace.