One-pass redundancy identification and removal

This paper presents a novel redundancy identification and removal algorithm for combinational circuits. The automatic test generator uses a special ordering of the target faults, and removes a redundant region as soon as an undetectable fault is encountered. Our strategy guarantees that a maximal region is removed without targeting any other faults in the same region, therefore minimizing the nuimber of redundant faults targeted. After the redundant region is removed, an additional analysis based on local implications identifies newly redundant faults that appear as a result of the removal. Then the process is repeated in turn for each of these newly redundant faults. Our approach removes all identified redundancies in one pass of test generation and fault simulation. Experimental results on benchmark circuits are reported.